Understand the materials and processes of glass substrates in one article

As a packaging substrate, the advantages of glass are very obvious. It is very flat and has a lower thermal expansion than organic substrates, simplifying the lithography process.



This is just the beginning. The growing warpage issues of multi-chip packages have been significantly improved. The chip can be hybridly bonded to the redistribution layer pad on the glass. Moreover, compared with organic core substrates, glass substrates provide extremely low transmission loss for high-frequency and high-speed devices.



To make matters worse, silicon interposers and organic core substrates are also losing momentum. Glass is much cheaper than silicon interposers, and the warpage is reduced by 50% and the positional accuracy is improved by 35%. This makes it easier to achieve redistribution layers (RDLs) with line widths and spacing of less than 2 microns, which is difficult to achieve with organic core substrates. In addition, the transparency of glass at communication wavelengths allows waveguides to be embedded in stacked glass structures for 6G applications. Ultra-thin (less than 100 microns) glass is easy to make in large sizes of 700 x 700 mm.



Glass, usually borosilicate glass or quartz glass, is also very flexible in its use. It can be used as a carrier, a core substrate for embedded components, a 3D stacking material, or a sealed cavity for sensors and MEMS. Glass has better electrical conductivity than organic matter, so it is able to conduct heat away from active devices more efficiently. Its coefficient of thermal expansion (CTE) can be adjusted between 3 and 10 ppm/°C, making it more compatible with low-end silicon or high-end PCBs.



Glass also excels in high-frequency applications. Due to its much lower dielectric constant than silicon (2.8 vs. 12) and low tangent loss, the transmission loss is several orders of magnitude lower than silicon, greatly improving signal integrity.



Over the years, glass has attracted much attention from the industry as a next-generation packaging substrate material due to its many advantages. One of its key features is the ability to achieve high interconnect density and RDL cabling below 2μm. "With the boom in AI computing over the past two years, the need to reduce cabling density to increase the speed of internal communication on SiP has become a focus of IC package research and development," said Frank Wei, technical manager at Disco Hi-Tec America.



However, not everything is perfect. Microcracks are difficult to avoid with glass cutting (monolith), and the challenge of repeatedly manufacturing thousands of fine-pitch glass vias (TGVs) prevents glass from reaching its full potential. Intel has invested heavily in glass substrates over the past decade and confirmed earlier this month that it is still advancing its glass project. Despite manufacturing hurdles, the prospect of improved quality of high-performance computing/AI chips is driving its rapid development, as confirmed by the Electronic Components & Technology Conference (ECTC) 2025 and other recent conferences, where researchers are making progress in the following areas:



Stacked glass with a data rate of > 100 GHz;



TGV etching by laser modification and HF etching;



direct laser etching, eliminating the need for subsequent etching;



Fabrication of a 6μm, >15 aspect ratio TGV;



Predictive yield models for optimizing overlays to accelerate FOPLP yield ramp-up;



The accumulation layer is gradually reduced at the separation interface to prevent glass breakage.



Stacked glass is used in high-frequency applications



Glass is ideal for 6G wireless communication networks due to its high frequency transmission and extremely low loss, which must support data rates > 100 GHz. Heterogeneous integration in stacked glass enables the integration of high-frequency front-end chips with low-loss interconnects into large-scale antenna arrays.



"By breaking down transceiver modules into individual functional chips, such as power amplifiers and frequency converters, these chips can be embedded in the core of the stacked substrate and interconnected vertically," said Li Xingchen, a doctoral student at Georgia Tech. "Process highlights of stacking 2" (50 x 50 mm) chips on a glass substrate include the integration of daisy-chain structures, good alignment between glass layers (3 microns), glass through-layer laser drilling, and copper filling.

The researchers selected an ABF (Ajinomoto additive film, Dk = 3.3, Df = 0.0044) as a low-k dielectric and glass binder and constructed an RDL-based coplanar waveguide on two layers (see Figure 1). Wideband electrical performance up to 220 GHz with a loss of only 0.3 dB.

The 100 μm thick glass panels are stacked on uncured ABF using flip chip bonding technology, which minimizes panel displacement when heated. ABF encapsulates the chip, and then another layer of uncured ABF (15 μm) is laminated on top glass and cured. Glass vias for signal transmission and heat dissipation are formed using laser processing, followed by V-shaped vias up to 130 μm and 100 μm pitch filled using adhesion promoters, electroless copper plating, and electrolytic plating. This method demonstrates potential as a 3D stacking method for 6G applications.



Through-Glass (TGV) process



Lasers play a pivotal role in the manufacturing process of TGVs. Richard Noack, Strategic Product Manager at LPKF Laser & Electronics, recently detailed how laser-induced deep etching (LIDE) technology can be improved for mass production. LIDE first laser modified borosilicate glass, changing its structure to make it easy to perform anisotropic etching.



The laser modification process uses a single laser pulse to destroy the composition of the glass. "The initial modification is less than 1 micron wide and can be described as a 'bubble chain,'" Noack said. "This gently modified etch rate is 100 times higher than the rest of the material."



Next, hydrofluoric acid (HF) is used for wet etching to create the desired shape (see Figure 2). LIDE has demonstrated the ability to etch glass vias as small as 3μm with a 5μm pitch.



To facilitate wet panel processing, Yield Engineering Systems (YES) has developed an automated multi-chamber immersion, rinsing, and drying equipment that can handle up to 12 glass panels measuring 510 x 515 mm. Venugopal Govindarajulu, Senior Director of the company, presented a wet etching method for creating high-AR glass vias designed for high-volume production.



The equipment can etch 25-100μm TGV at 130°C using commercially available glass materials at an etch rate of up to 80μm/hour. The laser process can be adjusted to the desired shape, such as cylindrical, hourglass-shaped, through-hole, or cavity.



The YES team determined that the etch rate and TGV curves are a function of the HF bath chemistry, acid concentration, and etch temperature and can be adjusted to achieve a 5:1 highly selective etching (etch rate modified area/etch rate untreated glass).



The hourglass shape is considered ideal for using copper PVD technology to achieve cavity-free filling. Wet etching baths range from 4:1 to 20:1 (200 μm thick glass) aspect ratios (depth/diameter). "In high-volume production environments, key considerations include: optimizing the chemical process to achieve higher etch rates; optimize fluid dynamics for uniform etching; and good temperature and flow control for process capability," says Govindarajulu.

Although LIDE is considered the leading process for glass vias, companies are exploring more environmentally friendly solutions that do not use toxic hydrofluoric acid (HF). Toshi Otsu and colleagues at the University of Tokyo have successfully machined 6μm wide and 25μm spacing holes on 100μm thick Asahi Glass ENA1 material. This method uses a collimated deep UV laser beam (257 nm) with different pulse energies and emission frequencies. "The use of ultrashort pulse lasers minimizes the thermal impact on the surrounding material, allowing for precise, clean processing," the authors say.

SEM cross-sections show that the height, depth, width ratio of the top aperture of the glass of the TGV is larger than the bottom aperture. Depths up to 260μm and aspect ratios between 20:1 and 25:1. (See Figure 3). Future research will explore how changing the numerical aperture of a laser affects the aperture.



R&D helps increase the output of glass core substrates



Whenever the industry considers new materials such as glass, simulation provides insight into the interactions between materials. It also helps to compare processes, such as which adhesion promoter interfaces best with glass or which PVD copper or electroless copper forms a better seed layer.



"When moving to new substrates such as glass, atomic modeling will be a key tool for predicting the behavior of interfaces formed when multiple layers of film are placed on glass substrates," said Anders Blom, principal solutions engineer at Synopsys. This provides direction for determining the focus direction and what needs to be paid attention to during the machining process before manufacturing begins. ”



Since glass is an amorphous material, it must be modeled with dozens of atoms, while materials like crystalline silicon only need two atoms to start modeling. "Recent advances in GPU-accelerated and machine learning algorithms allow us to build and run realistic models of such complex systems using a combination of fast force fields and accurate first-principles modeling," Blom noted.



Another tool that can help advance panel-level R&D and yield improvement is predictive yield modeling, especially for AI processors with HBM. John Chang, Application Development Manager at Onto Innovation, detailed a predictive yield model at ECTC with a special focus on stackup defects. "These components are expensive," he says, "so it's critical to maximize yield at every step and identify defects early to minimize losses." ”



Although glass core substrates significantly reduce pattern distortion and warping compared to organic core substrates, their presence can still affect the yield of fan-out panel-level processes (FOPLP). The Onto Innovation method uses offline metrology tools to measure chip shift and deformation, which are then combined with custom process parameters and machine learning algorithms to quickly reduce overlay defects on 510 x 515 mm panels. [1] "By leveraging predictive analytics and machine learning models, yield prediction technology can not only identify potential in-line process defects, but also recommend actionable solutions to optimize production parameters at an early stage, resulting in faster capacity ramp-ups," said Mr. Zhang.



Panel-level overlay errors typically exhibit a nonlinear pattern across the entire panel, with four different correction methods: global correction, area-based (e.g., 4 set-in errors per panel), chip-based correction, and point-by-point correction. Chip-based calibration achieves the highest yield, but calibration time reduces yield. For each panel, point-based correction exposes multiple chips with similar offset regions in each exposure, reducing the impact on yield while maintaining high yields. However, yield is often unsatisfactory with this optimization method alone.

To speed up the overlay improvement process, the team developed a method to simulate the change of final yield with different process parameters. "By leveraging this technology (the complete process in Figure 4), users can determine the optimal parameters through simulation and validate the predictions by running a qualified substrate," says Chang.



In addition, diagrams and histograms help identify overlapping issues early in a production FOPLP environment, accelerating the certification process and simplifying process optimization. "With FOPLP expected to grow significantly in the coming years, we believe yield prediction technology will provide a clear path to rapid production and high yield of FOPLP lithography technology." Professor Zhang said.



Prevents limescale



As we all know, glass is fragile. Microcracks are a major problem during handling and other operations, especially during cutting.



The failure of the glass core substrate during the cutting process is called "SeWaRe", which is derived from the Japanese word for "cracking the back". Frank Wei and Andrew Frederick of Disco conducted a study to investigate the causes of substrate cracking during cutting. The study used different thicknesses of bare borosilicate glass (125 mm, 200 mm, and 500 mm), as well as two types of laminated laminates on both sides of the glass, and finally found the best known method of damage minimization.



Disco's research shows that the dual-blade cutting method produces more chipping edges but smoother edges compared to laser-based monolithic methods (laser stealth cutting and laser-enhanced ablation filling). The monolithic chip size is 5 x 5 mm and 15 x 15 mm, respectively. Importantly, the laminate improves chip strength, and the use of a higher modulus dielectrics allows for optimal chip strength.



Finite element modeling (FEM) shows that edge chipping is caused by the sharpest microscopic defects, which are most stressed during cutting. The Disco team discovered that the SeWarRe defect occurs when the overlay extends to the edge of the segmented area. These defects can be eliminated by removing the stackup at the split edge section, which is known as the pullback method.

While the mainstream cutting process for glass panels is done after laminating layers on both sides of the substrate, Shun Mitarai and colleagues at Sony Semiconductor Solutions have explored a novel approach by embedding the cut substrate into an organic resin to provide edge protection. [2] They compared the cut glass core embedding process (SGEP) to traditional processes in the industry. "The traditional glass core substrate manufacturing process (CP) is simple to operate while maintaining large glass panels, but requires significant investment in the formation of double-sided interconnects and requires extensive equipment modifications to handle without damaging the glass."



The traditional process begins with TGV etching and metallization, followed by the core interconnect process. Next, the laminated layer is laminated and then monolithic. Finally, apply organic resin to each edge of the substrate.



Instead, SGEP cuts the substrate after the core interconnect is formed. This novel step involves embedding the glass core segment into the copper-clad laminate frame. The laminated layer is then laminated and finally the resin frame is cut.



Mitarai notes that this protection process for individual glass edges is complex. Double-sided lamination can effectively balance warpage due to the coefficient of thermal expansion (CTE) during single-sided machining. The single-wafer glass core embedding process enables single-sided processing and provides superior substrate protection. The next steps in this approach will include improving process compatibility with strict design rules and further improving yields.



Hybrid bonding on glass core



The flatness and positioning accuracy of the glass create new integration and process possibilities. "Unlike organic core substrates, glass core substrates are flat enough for copper-copper hybrid bonding," said John Lau, senior special projects assistant at Synsyn Electronics. [3] He pointed out that glass is not a subscenic substrate for organic cores. Instead, it complements existing materials as smaller RDL lines and spacing can be fabricated using silica dielectrics and a double mosaic process.



The Unimicron team demonstrated flip-chip bonding of the device to an organic core and a glass core substrate. They found that the flip-chip-bonded hybrid bond warped slightly more on the glass than the flip-chip bonded microbumps, but both were within acceptable limits. They attribute the lower warpage of the microbump to its performance as a shock absorber. The authors suggest that glass with a higher coefficient of thermal expansion (CTE) (10 ppm/°C) should be used when bonded to a PCB with a coefficient of thermal expansion (CTE) in the range of 18 ppm/°C.



conclusion



Businesses in the glass ecosystem are preparing for continued growth in chip and substrate sizes in multi-chip advanced packaging and are making significant progress. High-frequency etching after laser modification is the primary method for forming glass vias of different shapes and sizes, but direct laser etching with excimer lasers is a more environmentally friendly option if the process can achieve the through-hole shape required for subsequent copper filling.



If the polymer pullback can be performed continuously before cutting with a blade or laser, micro-cracks (SeWaRe) of the glass may be avoided during cutting. It seems that changing the cutting method can reduce microcracks, but not eliminate them.